The present invention relates to ferroelectric memory devices and particularly to memory cells and memory array architectures making use of ferroelectric depletion-mode field-effect transistors.
Ferroelectric materials are a class of materials that can be thought of as having electrical properties somewhat analogous to the magnetic properties of ferromagnetic materials. A uniaxial ferromagnetic material can be magnetized in one of two directions, and thereafter will retain a magnetic field in that direction even after the applied magnetic field is removed; similarly, a ferroelectric material can be xe2x80x9cpolarizedxe2x80x9d in either direction (by applying an electric field to it), and thereafter will retain an electric field in that direction, even after the applied electric field is removed.
Ferroelectric materials have been successfully integrated into integrated circuit processes, but this integration can have some drawbacks. Ferroelectric materials having sufficient thermal stability for integrated circuit processing often include incompatible metals that must be separated from a silicon substrate. Such ferroelectric materials also tend to be strong oxygen sources, increasing the risk of undesirable oxidation of adjacent materials. Additionally, ferroelectric materials generally can only withstand a finite number of polarization reversals before their performance degrades.
Ferroelectric memories exploit the properties of ferroelectric materials. These materials are useful in semiconductor memories as they have characteristics to provide a non-volatile memory function; after a ferroelectric material has been polarized in one direction, it will hold that polarization for an extended time without further power input. In contrast, dynamic random access memory (DRAM) requires periodic refresh to maintain its data value, thus losing its data value upon the removal of its power source.
Since the physics of ferroelectric floating-gate memories are similar to standard floating-gate memories (such as Flash memories), the sensing operation is correspondingly similar. Typically, floating-gate memories are sensed by detecting the activation/deactivation of the selected transistor in response to a given gate/source voltage. Although a typical floating-gate memory""s activation/deactivation state is dependent on a stored charge of its floating gate, and a ferroelectric floating-gate memory""s activation/deactivation state is dependent on a polarization of a ferroelectric layer, they both can exhibit this binary behavior.
At the microscopic scale, the ferroelectric material can be seen to be divided into domains. A domain is a volume within which the polarization of the material is uniform. Each domain can have only two stable polarization states. The magnitude of the polarization state of the bulk material is a composite of the individual domain polarization states.
FIG. 1 schematically shows a typical hysteresis curve 102 for a ferroelectric material. When the applied electric field E is increased to a positive value E1, the polarization of the material will increase to a value P1. When the applied positive field is subsequently removed, the polarization will fall back to a positive xe2x80x9cremanent polarizationxe2x80x9d value Pr. In a similar manner, when the applied electric field is increased in the opposite direction, to a negative value xe2x88x92E2, the polarization of the material will go to a negative value xe2x88x92P2. When the applied negative field is subsequently removed, the polarization will fall back to a negative remanent polarization value xe2x88x92Pr. Thus, the material can take either of two polarization states in the absence of an electric field, depending on how it has been affected by the previously applied field. For electrical circuit analysis, the polarization state of a ferroelectric film can be thought of in terms of surface charge density, i.e., as amount of charge per unit area (usually written as xe2x80x9c"sgr"xe2x80x9d). Curve 104 is an example of a minor hysteresis curve obtained when the same material is cycled between electrical potentials having insufficient magnitude to cause complete reversal of the polarization.
When an increasingly strong electric field is applied to a ferroelectric material, more and more of the domains will change their state to line up with the applied field. The electric field seen by any one domain is affected by the polarization states of the other domains which are nearby. Consequently, a full reversal of polarization requires not only some threshold energy level, but also some delay as individual domains align. This is inconvenient for ferroelectric memories, since it limits the write speed of any such memory. Moreover, in memories that use a destructive read, i.e., a read operation using a voltage sufficient to cause reversal of polarity, this phenomenon is also an important constraint on read access time as the data must be rewritten after sensing. This has been a problem with commercialization of ferroelectric memories, since it is highly desirable for ferroelectric memories to have access times approximately as fast as those for DRAM memories.
Designers are under constant pressure to provide higher-density, and thus smaller, semiconductor devices. Semiconductor real estate equates to cost, and more efficient use of that real estate generally leads to lower-cost devices.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate architecture and methods of operation of ferroelectric semiconductor memory devices.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Depletion-mode ferroelectric transistors are described herein for use as non-volatile memory cells. Such memory cells find use in non-volatile memory devices as well as other electronic systems having non-volatile memory storage. Various embodiments are described having ferroelectric transistors formed on a semiconductor layer overlying a bit line. By forming the transistors on this elevated semiconductor layer, the underlying substrate is usable for other components of a memory device, such as sensing devices and decoder circuits, thus facilitating higher-density devices. Because the transistors display bulk transport characteristics, they can be fabricated on polysilicon as the semiconductor layer despite relatively poor Sixe2x80x94SiO2 interfaces.
For one embodiment, the invention provides a ferroelectric memory cell. The memory cell includes a ferroelectric layer formed overlying a conductively-doped semiconductor layer, wherein the semiconductor layer is formed overlying a bit line. The memory cell further includes a control gate formed overlying the ferroelectric layer and coupled to a word line. The memory cell still further includes a first source/drain region formed in the semiconductor layer and a second source/drain region formed in the semiconductor layer. The first source/drain region is coupled to a program line. The second source/drain region is coupled to the bit line. For a further embodiment, the semiconductor layer is a silicon-containing layer and the first and second source/drain regions each contain a metal silicide. For a still further embodiment, the first and second source/drain regions are doped regions of the semiconductor layer having the same conductivity type, but a higher dopant level.
For another embodiment, the invention provides a memory cell. The memory cell includes a gate dielectric layer formed on a conductively-doped polysilicon layer, wherein the conductively-doped polysilicon layer is formed overlying a bulk insulator layer. The memory cell further includes a floating gate formed on the gate dielectric layer, a ferroelectric layer formed on the floating gate, and a control gate formed on the ferroelectric layer and coupled to a word line. The memory cell still further includes a metal silicide trace formed in the polysilicon layer as a first source/drain region and a metal silicide island formed in the polysilicon layer as a second source/drain region.
For a further embodiment, the invention provides a ferroelectric memory array. The memory array includes a plurality of program lines formed in a conductively-doped semiconductor layer, a plurality of bit lines formed below the semiconductor layer, a plurality of ferroelectric transistors formed on the conductively-doped semiconductor layer, and a plurality of word lines formed on the plurality of ferroelectric transistors. Each ferroelectric transistors has a first source/drain region coupled to a program line, a second source/drain region coupled to a bit line, and a control gate coupled to a word line.
The invention further provides apparatus, systems and methods of various scope.